1. Field of the Invention
The present invention relates to an apparatus, method and program for controlling a networked communication bus for use in a semiconductor chip.
2. Description of the Related Art
Recently, in the fields of built-in computers and general-purpose processors that use an SoC (System on Chip), there is a growing demand for semiconductor chips with enhanced performance. And as the performance of a semiconductor chip has been enhanced these days to meet such a demand, the number of bus masters to be connected to the communication bus on the chip has been increasing and the traffic control to be done on transfer data being transmitted and received through the bus has getting more and more complicated.
For example, the number of functions that a single cellphone terminal can provide by itself has been increasing year by year lately. Specifically, mobile phones of today allow the user to transmit and receive email messages, do Web browsing, and receive and view a so-called “one-seg(ment)” terrestrial digital broadcast. As dedicated ICs that perform part or all of the processing that realizes these various functions serve as bus masters, an appropriate traffic control needs to be done on the data being transmitted and received through a communication bus that connects all of those dedicated ICs together. Meanwhile, a multi-core configuration has been adopted more and more often these days for microprocessing unit (MPU) chips, too. To synchronize respective processor cores functioning as bus masters with each other and make those cores cooperate with each other, an appropriate traffic control also needs to be done on the data being transmitted and received through a communication bus that connects all of those processor cores together.
A conventional design for such a traffic control uses a bus control method for giving a pair of bus masters, to which data is being transferred, the right to use the bus by connecting together respective bus masters with a broad band lumped bus and by turning cross-bar switches. According to such a bus control method, a wiring delay will be caused because the bus needs to circumvent the circuit board. In addition, since the cross-bar switches have to be arranged, an additional area needs to be left for them and the power dissipation also increases by using such switches. On top of that, according to such a lumped bus design, the average bus use efficiency will not increase, the operating frequency of the bus will also rise, and more power will be eventually dissipated by the bus. This is because the operating frequency of the bus is determined so as to guarantee even the highest one of the data transfer rates required by those bus masters.
Thus, to overcome those problems with the lumped bus, a so-called “NoC (Network on Chip)” communication bus that functions as a network by itself has been developed and actually used these days.
For example, FIGS. 1(a) and 1(b) illustrate a configuration for a part of an NoC bus. Specifically, FIG. 1(a) illustrates an exemplary hardware connection and FIG. 1(b) is a schematic representation thereof. As shown in FIGS. 1(a) and 1(b), bus masters 1a, 1b and 1c, all of which are integrated together on a single chip 10, are connected to the same bus 3 by way of their associated bus controllers (R) 2. It should be noted that in all of the drawings attached to this application, the NoC bus is illustrated as in the schematic representation shown in FIG. 1(b).
FIG. 2 illustrates an exemplary configuration for an NoC bus for coupling together a number of bus masters that form a two-dimensional mesh. In this example, a bus controller R for performing a control on a data transfer route is provided for each of various bus masters including microprocessors, DSPs, memories and input/output circuits. And two adjacent ones of those bus controllers R are connected (i.e., linked) together with a short line.
In such a configuration, data can be transferred from a bus master on the transmitting end to a bus master on the receiving end through a number of different communication routes. For example, FIG. 3 illustrates three routes (1), (2) and (3) leading from the transmitting end to the receiving end.
Also, if there are multiple bus masters that provide the same function, then there will be multiple receiving ends and multiple routes leading to those receiving ends. For example, FIG. 4 illustrates three routes leading from one transmitting end to three different receiving ends (1), (2) and (3).
By choosing the best one of multiple candidate routes according to the load imposed on the bus, the data transfer latency of the overall chip and the operating frequency of the bus can be reduced. That is why a multi-route control technique that can maximize the performance of the NoC bus is needed.
Japanese Patent Publication No. 3816531 discloses a method for choosing one of multiple data transfer routes according to the status of a bus that connects multiple bus masters together. According to the technique disclosed in Japanese Patent Publication No. 3816531, data is transferred on a frame-by-frame basis from a bus master on the transmitting end to a bus master on the receiving end. If the frame transmitted has been received successfully at the receiving end, acknowledge data is returned. Otherwise, no acknowledge data is returned. Thus, if no acknowledge data is returned, the bus master on the transmitting end senses that the transfer of that frame has failed. In that case, the bus master changes the transfer routes into another one and re-transmits that frame through it. In this manner, communications can be continued. If any error has been detected in the header of the frame received, then the bus master on the receiving end discards that frame, and therefore, the bus master on the transmitting end never receives any acknowledge data in that case. Likewise, if the frame transfer latency on the data transfer route currently chosen is too long for the frame to arrive at the receiving end within a predetermined period of time, the bus master on the transmitting end cannot receive the acknowledge data within the predetermined time. Then, the routes also need to be changed. By changing the data transfer routes dynamically in this manner according to the status of the route currently used, communications can be made through a route with less transfer latency or error.
If the conventional multi-route control technique is adopted, the bus master on the transmitting end needs to choose the best route selfishly so as to optimize its own data transfer status by using the transfer latency and the situation of error generation as evaluation indices.
As a result, the flow rate of the data being transferred through the bus (or link) that connects the bus masters together may vary. This is because as multiple bus masters on the NoC compete with each other to get the best route available, some data transfer route or link resource will be scrambled for by a number of bus masters and data will have to be transferred from multiple different transmitting ends through only a few links.
Such non-uniformity causes the following three problems.
First of all, in a link with a high flow rate, the operational loads on bus controllers at both ends of that link become so heavy that the data transfer latency increases significantly. The latency of the data transfer between bus masters is a decisive factor that determines the operation rates of those bus masters. For example, when data is transferred between a processor and a memory, the memory access latency increases the overall length of wait cycles for the processor, which will lead to a decline in performing performance.
Secondly, the operating frequency of the bus should be increased so as to cope with the link with a high flow rate. However, the higher the operating frequency of the bus, the more difficult it is to control the wiring delay and the crosstalk and the greater the number of design or verification process steps.
Thirdly, the higher the operating frequency of the bus, the greater the power dissipated by a link. The power dissipation P of each of multiple transistors that form a link is represented by the following Equation (1):P=α·C·V2·f  (1)where α denotes the switching rate, C denotes the capacitance of the circuit, V denotes the supply voltage and f denotes the operating frequency.
Furthermore, by decreasing the operating frequency, the supply voltage can also be reduced as represented by the following Equation (2):
                    V        =                              C                                          (                                  1                  -                  η                                )                            γ                                ·                      f                          1                              γ                -                1                                                                        (        2        )            
In Equation (2), η denotes the ratio of the operating threshold voltage of the transistor to the supply voltage and γ denotes a constant that depends on the process rule. For example, if γ=2, a decrease in operating frequency will reduce the power dissipation to the third power. That is why depending on the degree of non-uniformity of the flow rate, the power dissipation of the link that should cope with a high transfer rate could be very large.